Various new failure mechanisms plague modern nanometer-scale integrated circuits. Reduced voltage swings, increased current consumption, the introduction of new materials, and unprecedented densities render such circuits increasingly sensitive to phenomena like local temperature variations within a chip, local power supply voltage variations, clock jitter, and small resistive/capacitive defects. A common theme among these effects is that they are not uncovered using conventional debug and test methods. In other words, failures due to these effects do not manifest themselves in conventional ways; rather, they are timing related. Simplistically, they affect the maximum speed at which a circuit can operate in its mission environment. In the present state of the art, conventional test methods do not cover timing-related faults effectively. Thus, the latter represent a significant risk of increased test escapes, which are defined as failing parts that are not caught before shipment, or increased reliability escapes, which are defined as functional parts that suffer from premature failure in the field.
To deal with the mentioned new integrity issues in digital chips, recent attempts have been made to enhance test coverage and reliability. An example relates to power supply measurement during debug and diagnosis. Some have attempted to integrate process monitors for this purpose, the most common embodiment of which is a ring oscillator. If the power supply voltage to a ring oscillator is reduced due to excessive IR drop, its oscillation frequency decreases. Counting the number of times a ring oscillator toggles over a certain duration reveals its oscillation frequency and consequently the amount of power supply drop that it suffers from.
When it comes to testing chips in large volume, ring-oscillator monitors become ineffective since they require calibration and offer too little resolution. During production test, delay faults, which are timing-related faults that result from the various signal integrity issues identified earlier, necessarily need to be addressed another way. In the present state of the art, software-based automated test pattern generation and over-clocking techniques are used. Small delay faults are notorious in that they pass conventional structural test methods without being detected. That is, test vectors created using conventional test pattern generation techniques do not fail even if a timing-related defect actually exists in the manufactured component. To deal with this, engineers commonly excite a device under test with the same conventional test vectors, but they run them at speeds that may exceed the nominal functional speed. Monitoring vectors that pass at low speed and fail at high speed gives insights into possible delay faults. Unfortunately, a failing over-speed vector does not necessarily mean the part being tested is really defective since the latter was not designed to operate at this fast clock frequency in the first place.